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HA-2420, HA-2425
Data Sheet November 19, 2004 FN2856.6
3.2s Sample and Hold Amplifiers
The HA-2420 and HA-2425 is a monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and JFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-and-hold circuit is formed. When the switch is closed, the device behaves as an operational amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. For more information, please see Application Note AN517..
Features
* Maximum Acquisition Time - 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . 4s (Max) - 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . 6s (Max) * Low Droop Rate (CH = 1000pF). . . . . . . . . . 5V/ms (Typ) * Gain Bandwidth Product . . . . . . . . . . . . . . . 2.5MHz (Typ) * Low Effective Aperture Delay Time . . . . . . . . . 30ns (Typ) * TTL Compatible Control Input * 12V to 15V Operation
Applications
* 12-Bit Data Acquisition * Digital to Analog Deglitcher * Auto Zero Systems * Peak Detector * Gated Operational Amplifier
Pinout
HA-2420 (CERDIP) HA-2425 (PDIP) TOP VIEW
-IN 1 +IN 2 14 S/H CONTROL 13 GND 12 NC 11 HOLD CAP. 10 NC 9 V+ 8 NC
Ordering Information
PART NUMBER HA1-2420-2 HA3-2425-5 TEMP. RANGE (oC) -55 to 125 0 to 75 PACKAGE 14 Ld CERDIP 14 Ld PDIP PKG. DWG. # F14.3 E14.3
OFFSET ADJ. 3 OFFSET ADJ. 4 V- 5 NC 6 OUTPUT 7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HA-2420, HA-2425
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V Digital Input Voltage (Sample and Hold Pin) . . . . . . . . . . +8V, -15V Output Current . . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Ceramic Packages). . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range HA-2420-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-2425-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . 12V to 15V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions (Unless Otherwise Specified) VSUPPLY = 15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) TEST CONDITIONS TEMP. (oC) HA-2420-2 MIN TYP MAX MIN HA-2425-5 TYP MAX UNITS
PARAMETER INPUT CHARACTERISTICS Input Voltage Range Offset Voltage
Full 25 Full
10 5 10
2 3 40 10 10 -
4 6 200 400 50 100 -
10 5 10
3 4 40 10 10 -
6 8 200 400 50 100 -
V mV mV nA nA nA nA M V
Bias Current
25 Full
Offset Current
25 Full
Input Resistance Common Mode Range TRANSFER CHARACTERISTICS Large Signal Voltage Gain Common Mode Rejection Hold Mode Feedthrough Attenuation (Note 2) Gain Bandwidth Product (Note 2) OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Full Power Bandwidth (Note 2) Output Resistance TRANSIENT RESPONSE Rise Time (Note 2) Overshoot (Note 2) Slew Rate (Note 2) VO = 200mVP-P VO = 200mVP-P VO = 10VP-P VO = 20VP-P DC RL = 2k RL = 2k, VO = 20VP-P VCM = 10V fIN 100kHz
25 Full
Full Full Full 25
25 80 -
50 90 -76 2.5
-
25 74 -
50 90 -76 2.5
-
kV/V dB dB MHz
Full 25 25 25
10 15 -
100 0.15
-
10 15 -
100 0.15
-
V mA kHz
25 25 25
3.5
75 25 5
100 40 -
3.5
75 25 5
100 40 -
ns % V/s
2
FN2856.6 November 19, 2004
HA-2420, HA-2425
Electrical Specifications
Test Conditions (Unless Otherwise Specified) VSUPPLY = 15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued) TEST CONDITIONS TEMP. (oC) HA-2420-2 MIN TYP MAX MIN HA-2425-5 TYP MAX UNITS
PARAMETER DIGITAL INPUT CHARACTERISTICS Digital Input Current
VIN = 0V VIN = 5V
Full Full Full Full
2.0
-
-0.8 20 0.8 -
2.0
-
-0.8 20 0.8 -
mA A V V
Digital Input Voltage
Low High
SAMPLE AND HOLD CHARACTERISTICS Acquisition Time (Note 2) Acquisition Time (Note 2) Hold Step Error Hold Mode Settling Time Aperture Time (Note 3) Effective Aperture Delay Time Aperture Uncertainty Drift Current (Note 2) HA1-2420 HA1-2425 HA3-2425, HA4P2425, HA9P2425 POWER SUPPLY CHARACTERISTICS Supply Current (+) Supply Current (-) Power Supply Rejection NOTES: 2. AV = 1, RL = 2k, CL = 50pF. 3. Derived from computer simulation only; not tested. 25 25 Full 80 3.5 2.5 90 5.5 3.5 74 3.5 2.5 90 5.5 3.5 mA mA dB VIN = 0V To 0.1% 10V Step To 0.01% 10V Step VIN = 0V To 1mV 25 25 25 25 25 25 25 25 Full Full Full 2.3 3.2 10 860 30 30 5 5 1.8 4 6 20 10 2.3 3.2 10 860 30 30 5 5 0.1 7.5 4 6 20 1.0 10.0 s s mV ns ns ns ns pA nA nA nA
Functional Diagram
OFFSET ADJUST V+ 3 4 9
-INPUT +INPUT S/H CONTROL
1 2 14
+
+ HA-2420/2425
7
OUT
13 GND V-
5
11 HOLD CAPACITOR
3
FN2856.6 November 19, 2004
HA-2420, HA-2425 Test Circuits and Waveforms
-IN INPUT +IN S/H CONTROL HOLD CAP GND
OUTPUT S/H CONTROL HOLD SAMPLE
OUTPUT CH S/H CONTROL INPUT VSTEP
NOTE: Set rise/fall times of S/H Control to approximately 20ns. FIGURE 2. HOLD STEP ERROR TEST
FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT
SINE WAVE INPUT IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1
+5V EN HI-508A MUX OUT HA-2420/2425 OUT +IN S/H HOLD CONTROL CAP GND VINP-P A0 CH
-IN
VO
S/H CONTROL
HOLD SAMPLE
OUTPUT
V
t
S/H CONTROL INPUT
NOTE: Compute hold mode feedthrough attenuation from the formula: V OUT HOLD Feedthrough Attenuation = 20 log --------------------------------V IN HOLD Where VOUTHOLD = Peak-to-Peak value of output sinewave during the hold mode. FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
NOTE: Measure the slope of the output during hold, V/t, and compute drift current from: ID = CH V/t. FIGURE 3. DRIFT CURRENT TEST
4
FN2856.6 November 19, 2004
HA-2420, HA-2425 Schematic Diagram
OFFSET ADJ. V+
Q89 Q5 Q17 Q106 Q82 Q90 Q2 Q4 Q23
R1 Q29
R2 Q30 Q58 J63
Q64 Q65 Q66 Q72
Q45 RP Q7 Q105 Q15 Q11 Q6 Q47 Q49 D1 Q8 Q
19
Q46
Q59 J61 Q73
Q74
Q9
Q91 Q87 Q51 Q48 R7 Q53 Q54 Q50 Q75 Q31 Q32 Q100 Q101 Q56 Q76 C4 J60 Q67 Q68 Q78 Q70 Q102 Q62 R13 Q81 +IN -IN VQ71 Q80 R14 Q79 Q69 R10 Q77 Q55 Q26 C3 15pF R8 R9 OUT Q27 Q21 Q20 Q52 CH
Q3 Q10
Q18 Q13 Q22 Q83
Q24 Q25
Q33 Q34 Q38 Q35
S/H CONTROL
GND Q12
Q14 R11 Q103
R121 GND J86 J57
Q39 Q42
Q40 Q43
Q83 Q41 Q44
Q16
5
FN2856.6 November 19, 2004
HA-2420, HA-2425 Application Information
HOLD STEP VOLTAGE (mV) +10 5 -10 -5 0 -5 -10 -15 -20 -25 -30 -35 CH = 100pF RI 0.002RI RF S/H CONTROL INPUT CH = 10,000pF CH = 1000pF INPUT +IN -IN S/H CONTROL OUT OUTPUT DC INPUT VOLTAGE (V) CH = 0.1F S/H CONTROL INPUT +5 +10 INPUT RI -IN +IN S/H CONTROL OUT RF 0.002RF OUTPUT
-RF NOTE: GAIN ---------RI
FIGURE 6. INVERTING CONFIGURATION
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
RF NOTE: GAIN ~ 1 + ------RI
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be adjusted using a 100k trim pot, as shown in Figure 8. The recommended adjustment procedure is: Apply 0V to the sample-and-hold input, and a square wave to the S/H control. Adjust the trim pot for 0V output in the hold mode.
FIGURE 7. NON-INVERTING CONFIGURATION
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10NOMINAL). Adjust the trim pot for an output hold voltage of
( V - 10 NOMINAL ) + ( -10V ) ----------------------------------------------------------------2
Figure 8 shows a typical unity gain circuit, with Offset Zeroing. All of the other normal op amp feedback configurations may be used with the HA-2420, HA-2425. The input amplifier may be used as a gated amplifier by utilizing Pin 11 as the output. This amplifier has excellent drive capabilities along with exceptionally low switch leakage.
CONTROL CH V+
+
+
-
IN
V-
OUT
100k OFFSET TRIM (25mV RANGE)
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
The method used to reduce leakage paths on the PC board and the device package is shown in Figure 9. This guard ring is recommended to minimize the drift during hold mode. The hold capacitor should have extremely high insulation resistance and low dielectric absorption. Polystyrene (below 85oC), Teflon, or Parlene types are recommended. For more applications, consult Intersil Application Note AN517, or the factory applications group.
6
FN2856.6 November 19, 2004
HA-2420, HA-2425
CONTROL GND -IN HOLD CAPACITOR +IN
Effective Aperture Delay Time (EADT)
The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command.
OUT V+
V-
Aperture Uncertainty
The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data.
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
Glossary of Terms
Acquisition Time
The time required following a "sample" command, for the output to reach its final value within 0.1% or 0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time.
Drift Current
The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula:
V I D (pA) = C H (pF) x ------- (V s ) t
Aperture Time
The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is that interval between the conditions of 10% open and 90% open.
7
FN2856.6 November 19, 2004
HA-2420, HA-2425 Typical Performance Curves
1000 1000 MIN. SAMPLE TIME DRIFT DURING HOLD FOR 0.1% ACCURACY AT 25oC (mV/s) 10V SWINGS (s) NOISE (VRMS) UNITY GAIN PHASE MARGIN (DEGREES) 10 HOLD STEP OFFSET ERROR (mV) 100 OUTPUT NOISE "HOLD" MODE EQUIV. INPUT NOISE "SAMPLE" MODE - 100k SOURCE RESISTANCE
100
1.0
UNITY GAIN BANDWIDTH (MHz) SLEW RATE (V/s) 10pF 100pF 0.01F 1000pF CH VALUE 0.1F 1.0F
10 EQUIV. INPUT NOISE "SAMPLE" MODE - 0 SOURCE RESISTANCE 1 10
0.1
0.01
100 1K 10K 100K BANDWIDTH (LOWER 3dB FREQUENCY = 10Hz)
1M
FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLDING CAPACITOR
FIGURE 11. BROADBAND NOISE CHARACTERISTICS
1000 OPEN LOOP VOLTAGE GAIN (dB)
100 ID (pA)
10
1 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125
100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 10
CH = 100pF CH = 1000pF CH = 0.01F
CH = 1.0F CH = 0.1F
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. DRIFT CURRENT vs TEMPERATURE
FIGURE 13. OPEN LOOP FREQUENCY RESPONSE
OPEN LOOP PHASE ANGLE (DEGREES)
-30 CH = 1000pF -40 ATTENUATION (dB) -50 -60 -70 -80 -90
0 20 40 60 80 100 120 140 160 180 200 220 240 10 100
CH = 0.01F CH = 1000pF CH 100pF CH = 1.0F
CH = 0.1F
100
1K
10K
100K
1M
10M
1K
10K
100K
1M
10M
100M
10V SINUSOIDAL INPUT FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 14. HOLD MODE FEED THROUGH ATTENUATION
S/H CONTROL SAMPLE HOLD
FIGURE 15. OPEN LOOP PHASE RESPONSE
4V 0V
8
FN2856.6 November 19, 2004
HA-2420, HA-2425 Typical Performance Curves
S/H (5V/DIV.)
(Continued)
S/H (5V/DIV.)
0V
+10V
VOUT (2V/DIV.)
VOUT (2V/DIV.)
-10V
0V
TIME (1s/DIV)
TIME (1s/DIV)
FIGURE 16. ACQUISITION TIME (CH = 1000pF)
FIGURE 17. ACQUISITION TIME (CH = 1000pF)
S/H (5V/DIV.)
S/H (5V/DIV.)
0V
+1V VOUT (0.5V/DIV.)
VOUT (0.5V/DIV.) -1V 0V
TIME (1s/DIV)
TIME (1s/DIV)
FIGURE 18. ACQUISITION TIME (CH = 1000pF)
FIGURE 19. ACQUISITION TIME (CH = 1000pF)
S/H (5V/DIV.) S/H (5V/DIV.) 0.1V
0V 0V
VOUT (50mV/DIV.) -0.1V
VOUT (50mV/DIV.)
TIME (500ns/DIV)
TIME (500ns/DIV)
FIGURE 20. ACQUISITION TIME (CH = 1000pF)
FIGURE 21. ACQUISITION TIME (CH = 1000pF)
9
FN2856.6 November 19, 2004
HA-2420, HA-2425 Die Characteristics
DIE DIMENSIONS: 102 mils x 61 mils x 19 mils 2590m x 1550m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA SUBSTRATE POTENTIAL: VBACKSIDE FINISH: Gold, Nickel, Silicon, etc. PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA TRANSISTOR COUNT: 78 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
+IN IN
HA-2420, HA-2425
GND
VOS ADJ
VOS ADJ
HOLD CAP
V-
V+
OUTPUT
10
FN2856.6 November 19, 2004
HA-2420, HA-2425 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
11
FN2856.6 November 19, 2004
HA-2420, HA-2425 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN2856.6 November 19, 2004

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